The invention relates to a digitally controlled switched-mode voltage convertor comprising conversion means including switching means for the purpose of converting an input voltage into an output voltage; and control means for controlling a duty cycle of the switching means in steps having discrete values.
Such a voltage convertor is known from German Patent Specification 2746578. In said converter the desired output voltage is obtained by the stepwise control of the duty cycle of a switch (i.e. the time during which the switch is closed divided by the sum of the time during which the switch is closed and the time during which the switch is open). For example, if the output voltage is to be raised the duty cycle is increased in steps.
A disadvantage of the known convertor is that the accuracy of the output voltage, i.e. the voltage resolution, is limited in that the voltage resolution is correlated with the time resolution of the voltage convertor, which time resolution is defined by the duty cycle, which can be adapted in discrete steps.
In the known voltage convertor the voltage resolution can be improved by reducing the step size of the discrete steps by a given factor. For a similar voltage range of the output voltage the number of discrete steps should then be increased by the same factor. This means that if the duty cycle of the switch is minimum, which occurs at the smallest possible value of the output voltage, the value of the duty cycle has been reduced by the above-mentioned factor. However, the maximum value of the duty cycle, which occurs at the largest possible value of the output voltage, does not change. It follows that the ratio between the maximum value of the duty cycle and the minimum value of the duty cycle has (potentially) increased by the above-mentioned factor. The shortest time during which the switch is closed (during the minimum value of the duty cycle) dictates the maximum period of a system clock that is required. This maximum period corresponds to a minimum system clock frequency of the system clock. It will be evident that in an attempt to improve the voltage resolution, by reducing the step size of the discrete steps (or by increasing the time resolution) by a given factor, the minimum system clock frequency increases by this given factor.
The above solution is disadvantageous because, in order to enable the voltage resolution to be made sufficiently high, the minimum required system clock frequency could be so high that the electronic circuitry required for this purpose is highly intricate, dissipates much power, or is even impracticable. A solution for this is to increase the switching period of the switch, i.e. the sum of the time that the switch is closed and the time that the switch is open, without the duty cycle being changed. In that case the minimum system clock frequency can be reduced proportionally. Phrased differently, the minimum system clock frequency is directly proportional to the minimum switching frequency (the reciprocal of the switching period of the switch).
However, the above-mentioned solution has another disadvantage. Switched-mode voltage convertors generally include a coil. The energy losses of the voltage convertor, for a given duty cycle, are then inversely proportional to the value of the self-inductance of the coil, and inversely proportional to the switching frequency. Since the self-inductance cannot be arbitrarily large in view of the coil dimensions, the efficiency of the voltage convertor will be lower in the case of a reduced switching frequency.
Summarizing, it can be stated that increasing the voltage resolution of the voltage convertor by increasing the time resolution is subject to limits imposed by a minimum system clock frequency, on the one hand, and a maximum system clock frequency, on the other hand.
Furthermore, it is to be noted that the capacitance of a smoothing capacitor, which is generally present, should be higher as the switching frequency decreases. This results in an undesirable increase in the size of the smoothing capacitor.